Title :
A hybrid built-in self-test scheme for DRAMs
Author :
Chi-Chun Yang ; Jin-Fu Li ; Yun-Chao Yu ; Kuan-Te Wu ; Chih-Yen Lo ; Chao-Hsun Chen ; Jenn-Shiang Lai ; Ding-Ming Kwai ; Yung-Fa Chou
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Abstract :
This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.
Keywords :
DRAM chips; built-in self test; finite state machines; firmware; FSM-based controller; JEDEC wideIO DRAM; configuration parameters; dynamic random access memory; finite state machines; hybrid BIST scheme; hybrid built-in self-test scheme; in-field programmability; metal changing; microcode-based controller; microcodes; support march and nonmarch test algorithms; Algorithm design and analysis; Built-in self-test; Generators; Radiation detectors; Random access memory; Read only memory; Registers;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2015.7114502
