Title : 
A test-application-count based learning technique for test time reduction
         
        
            Author : 
Guo-Yu Lin ; Kun-Han Tsai ; Jiun-Lang Huang ; Wu-Tung Cheng
         
        
            Author_Institution : 
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
         
        
        
        
        
        
            Abstract : 
One popular adaptive test approach is to reorder the test patterns according to their fault detection performance - by applying the more effective patterns first, the total test time can be significantly reduced. While very effective, the detection performance based approach fails to identify some high-quality test patterns and leaves them unused throughout the test application process. In this paper, we propose a test-application-count based learning technique to help identify high-quality test patterns. By ensuring that all patterns are applied for at least the specified number of times, the proposed technique finds more high-quality test patterns and moves them to the front of the test pattern list. Experimental results show that the proposed test-application-count based learning technique achieves 52% test time reduction (TTR) in average - a 12% improvement compared to the detection performance based approach.
         
        
            Keywords : 
fault diagnosis; integrated circuit testing; TTR; adaptive test approach; fault detection performance based approach; high-quality test patterns; test time reduction; test-application-count based learning technique; Automatic test pattern generation; Fault detection; Fault diagnosis; Indexes; Manufacturing; Robustness;
         
        
        
        
            Conference_Titel : 
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
         
        
            Conference_Location : 
Hsinchu
         
        
        
            DOI : 
10.1109/VLSI-DAT.2015.7114507