Efficient Realization of Large Integer Multipliers and Squarers

This paper presents an efficient design methodology and a systematic approach for the implementation of multiplication and squaring function for large integers using small-size embedded multipliers. A general architecture of the multiplier and squarer is proposed as well as a set of equations is derived to aid in the realization. The inputs of the multiplier and squarer are split into several segments leading to an efficient utilization of the small-size embedded multipliers and a reduced number of required addition operations. Various benchmarks were tested for different segments ranging from 2 to 4 targeting Xilinx Spartan-3 FPGA. The synthesis was performed with the aid of the Xilinx ISE 7.1 XST tool. Our approach was compared with the traditional technique using the same tool. The results illustrate that our design approach is very efficient in terms of both timing and area saving. The combinational delay is reduced by an average of 6.1% for the multiplier and 15.5% for the squarer. The area saving, in terms of number of 4-input LUTs, is about 8.3% for the multiplier and 50% for the squarer. In the case of the multiplier, both the approaches use the same number of embedded multipliers. For the squarer, our proposed approach has reduced the number of required embedded multipliers by an average of 30.5% compared to the traditional technique