DocumentCode :
2727685
Title :
Real Time ELA De-Interlacing with the Xtensa Reconfigurable Processor
Author :
Mohammadi, Hossein Mahvash ; Savaria, Yvon ; Langlois, J. M Pierre
Author_Institution :
Dept. of Electr. Eng., Ecole Poly technique de Montreal, Que.
fYear :
2006
fDate :
38869
Firstpage :
25
Lastpage :
28
Abstract :
This paper proposes optimization techniques to accelerate the enhanced edge-based line average (ELA) de-interlacing method. ELA is based on edge detection and directional interpolation as well as median filtering. The techniques are first based on low-level software optimizations to accelerate loops and arithmetic operations. Specialized hardware structures and corresponding new instructions are then defined for the Xtensa reconfigurable processor to accelerate ELA-specific operations. The combined software and hardware techniques result in a speed-up of 67x when compared to a base case. This accelerates the processing time from 25 times slower than real time to 2.7 times faster for a NTSC frame rate. A parallel processing version of ELA is also discussed
Keywords :
digital signal processing chips; edge detection; parallel processing; Xtensa reconfigurable processor; arithmetic operations; directional interpolation; edge detection; edge-based line average de-interlacing method; low-level software optimizations; median filtering; parallel processing version; Acceleration; Arithmetic; Filtering; HDTV; Hardware; Image edge detection; Interpolation; Optimization methods; Process design; TV;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006 IEEE North-East Workshop on
Conference_Location :
Gatineau, Que.
Print_ISBN :
1-4244-0416-9
Electronic_ISBN :
1-4244-0417-7
Type :
conf
DOI :
10.1109/NEWCAS.2006.250906
Filename :
4016937
Link To Document :
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