Parasitic-aware Delay Optimization for Multi-GHz Static CMOS Ring Oscillators

Author

Karam, Victor ; Fong, Neric ; Plett, Calvin

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont.

fYear

2006

fDate

18-21 June 2006

Firstpage

101

Lastpage

104

Abstract

A method for optimizing the oscillation frequency of a multi-GHz ring oscillator composed of static CMOS inverters is derived. The derivation is based on the propagation delay of each inverter stage, and it includes the effects of interconnect parasitics and gate resistance. The method was verified with a 90-nm SOI CMOS process through layout extraction and simulation for predicting the underlying factors in delay as the inverter´s devices were scaled

Keywords

CMOS digital integrated circuits; delays; integrated circuit modelling; invertors; oscillators; silicon-on-insulator; 90 nm; CMOS digital integrated circuits; SOI; gate resistance; interconnect parasitics; multi GHz ring oscillator; parasitic-aware delay optimization; propagation delay; static CMOS inverters; CMOS digital integrated circuits; Circuit simulation; Foundries; Frequency; Integrated circuit interconnections; Inverters; Optimization methods; Propagation delay; Ring oscillators; Semiconductor device testing; CMOS digital integrated circuits; SOI; delay; propagation; ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006 IEEE North-East Workshop on

Conference_Location

Gatineau, Que.

Print_ISBN

1-4244-0416-9

Electronic_ISBN

1-4244-0417-7

Type

conf

DOI

10.1109/NEWCAS.2006.250910

Filename

4016941