Implementation of Hardware Multithreading in a Pipelined Processor

This paper outlines requirements for introducing hardware support for multithreading in a pipelined 32-bit processor that has been used for prototyping single-chip multiprocessor implementations in programmable logic. The inclusion of multithreading within a processor complements the use of multiple processor instances by enabling multiple execution contexts to share a single processor with fast hardware-supported context switching, in addition to having multiple contexts executing in parallel on distinct processors. New instructions for thread management are described, and modifications to the existing processor for supporting up to eight threads are outlined. Synthesis results obtained using Altera Quartus II for a Stratix logic chip indicate an overhead of 21% for multithreading in terms of logic elements, with the largest contribution from multiple program counters and the associated logic to multiplex their outputs and set their contents. There is no additional overhead related to embedded memory blocks because previously-unused storage is allocated to distinct register files for multiple threads. From the initial experience of developing enhancements for multithreading, future work will refine the support for multithreading and apply this capability in multiprocessor implementations