Title :
Digital Encoders for High Speed Flash-ADCs: Modeling and Comparison
Author :
Ali, Syed Masood ; Raut, Rabin ; Sawan, Mohamad
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que.
Abstract :
Digital encoders are a known bottleneck for high speed flash-ADC architectures. This paper describes a survey of various thermometer-to-binary code (TC-to-BC) decoders. Wallace tree decoder is found to be the best among others in terms of bubble error correction but it consumes more power for multigiga hertz applications. Authors present that TC-to-BC decoder based on feedforward neural network structure cascaded with bit-swapping technique can achieve almost same level of performance for bubble error correction and consumes less power. The proposed implementation is suitable for CMOS process technology which is considered very economic solution in integrated circuits (IC) process industry
Keywords :
CMOS integrated circuits; analogue-digital conversion; binary codes; decoding; encoding; error correction; feedforward neural nets; tree codes; CMOS process technology; Wallace tree decoder; analog-to-digital converters; bubble error correction; digital encoders; feedforward neural network; integrated circuits process industry; thermometer-to-binary code decoders; CMOS integrated circuits; CMOS process; CMOS technology; Decoding; Error correction; Feedforward neural networks; Industrial economics; Integrated circuit technology; Neural networks; Power generation economics;
Conference_Titel :
Circuits and Systems, 2006 IEEE North-East Workshop on
Conference_Location :
Gatineau, Que.
Print_ISBN :
1-4244-0416-9
Electronic_ISBN :
1-4244-0417-7
DOI :
10.1109/NEWCAS.2006.250923
