Title :
Storage hierarchy to support a 600 MHz G5 S/390 microprocessor
Author :
Turgeon, P.R. ; Pak-Kin Mak ; Plass, D. ; Blake, M. ; Fee, M. ; Fischer, M. ; Ford, C. ; Holmes, G. ; Jackson, K. ; Jones, C. ; Kark, K. ; Malgioglio, F. ; Meaney, P. ; Pell, E. ; Scarpero, W. ; Seigler, A.R. ; Shen, W. ; Strait, G. ; Vanhuben, G. ; Wellw
Author_Institution :
IBM Corp., Poughkeepsie, NY, USA
Abstract :
Although a microprocessor´s maximum frequency and internal design are important, the storage hierarchy is the primary reason for the large system performance improvement of the S/390 G5 compared to the G4. The improvement is achieved with an L2 cache, system controller and memory interface clocked at 1/4 the microprocessor frequency.
Keywords :
cache storage; integrated circuit design; microprocessor chips; semiconductor storage; 600 MHz; G5 S/390 microprocessor; L2 cache; memory interface; storage hierarchy; system controller; system performance improvement; Control systems; Microprocessors; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759132
