A Fully Differential 24GHz Transmit PLL in a 0.13μm CMOS Technology

Author

Shang, Hao ; Rogers, John W M ; Chiu, James

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont.

fYear

2006

fDate

18-21 June 2006

Firstpage

45

Lastpage

48

Abstract

This paper describes the design of a transmit PLL circuit at 24GHz in a 0.13mum CMOS technology. This transmit PLL is made with fully differential circuits to reject common mode noise. The VCO output frequency is 24GHz and the IF frequency is 400 MHz. In order to take advantage of the fully differential VCO, a differential charge pump and loop filter are developed. This differential charge pump draws no DC current when PLL is in lock. The supply voltage for this PLL is 1.5V. The loop bandwidth is 500 KHz and the in band phase noise at 100 KHz offset is -112dBc. The settling time is 220 ns

Keywords

CMOS integrated circuits; filters; integrated circuit design; phase locked loops; phase noise; voltage-controlled oscillators; 0.13 micron; 100 kHz; 220 ns; 24 GHz; 400 MHz; CMOS technology; PLL circuit; VCO; common mode noise; differential charge pump; fully differential circuits; loop filter; phase noise; Bandwidth; CMOS technology; Charge pumps; Circuit noise; Filters; Frequency; Phase locked loops; Phase noise; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006 IEEE North-East Workshop on

Conference_Location

Gatineau, Que.

Print_ISBN

1-4244-0416-9

Electronic_ISBN

1-4244-0417-7

Type

conf

DOI

10.1109/NEWCAS.2006.250932

Filename

4016963