DocumentCode
2728228
Title
A sub-40 ns random-access chain FRAM architecture with a 768 cell-plate-line drive
Author
Takashima, D. ; Shuto, S. ; Kunishima, I. ; Takenaka, H. ; Oowaki, Y. ; Tanaka, S.
Author_Institution
Res. & Dev. Center, Toshiba Corp., Yokohama, Japan
fYear
1999
fDate
17-17 Feb. 1999
Firstpage
102
Lastpage
103
Abstract
This work demonstrates a prototype of nonvolatile chain ferroelectric RAM (chain FRAM), with fast compact cell-plate-line drive. A 16 kb chain FRAM test chip using 0.5 /spl mu/m 2-metal CMOS achieves 37 ns random-access time and 80 ns read/write cycle time at 3.3 V.
Keywords
CMOS memory circuits; ferroelectric storage; memory architecture; random-access storage; 0.5 micron; 16 kbit; 3.3 V; 37 ns; 7 ns; 80 ns; FRAM architecture; cell-plate-line drive; nonvolatile chain ferroelectric RAM; random-access chain FRAM; read/write cycle time; two-metal CMOS; Capacitors; Current supplies; Delay; Ferroelectric films; Ferroelectric materials; Nonvolatile memory; Power supplies; Random access memory; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-5126-6
Type
conf
DOI
10.1109/ISSCC.1999.759147
Filename
759147
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