A 0.5 /spl mu/m 3 V 1T1C 1 Mb FRAM with a variable reference bitline voltage scheme using a fatigue-free reference capacitor

Author

Miyakawa, T. ; Tanaka, S. ; Itoh, Y. ; Takeuchi, Y. ; Ogiwara, R. ; Doumae, S.M. ; Takenakal, H. ; Kunishima, I. ; Shuto, S. ; Hidaka, O. ; Ohtsuki, S. ; Tanaka, S.-I.

Author_Institution

USLI Device Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

104

Lastpage

105

Abstract

Ferroelectric random access memory (FRAM/sup (R)/) has been intensively studied because of its high potential for low-power, high-speed operation and high switching endurance. The 2-transistor 2-capacitor (2T2C) cell structure offers stable read, however, it is not suitable for a high-density memory because of the larger cell area. The 1-transistor 1-capacitor (1T1C) cell structure is expected to be the key technology for realizing a megabit FRAM.

Keywords

cellular arrays; ferroelectric capacitors; ferroelectric storage; high-speed integrated circuits; low-power electronics; random-access storage; 0.5 micron; 1 Mbit; 3 V; FRAM; fatigue-free reference capacitor; ferroelectric random access memory; high-speed operation; low-power operation; one-transistor one-capacitor cell structure; switching endurance; variable reference bitline voltage scheme; Driver circuits; Fatigue; Ferroelectric films; Ferroelectric materials; MOS capacitors; Nonvolatile memory; Operational amplifiers; Power generation; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759150

Filename

759150