A 622 Mb/s CMOS ATM switch access LSI with maintenance cycle interleaved pipeline architecture

Author

Saito, Takashi ; Shimojo, Y. ; Nagamatsu, Takashi ; Hasegawa, Junichi ; Fujisawa, T. ; Miyama, Y. ; Yoshida, Norihiro ; Oyamada, Yuji ; Irie, Hidetsugu ; Shinohara, K. ; Hanagama, Y. ; Sakaue, K. ; Satoh, Kei ; Hayashida, Hideki ; Sasaki, T. ; Baba, H. ;

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

168

Lastpage

169

Abstract

A switch access LSI with multiple ports (SAM) functions as an interface to the switch fabric. The SAM and two other chips, a switch element (SE) and a distributor/arbiter (DA), constitute a chipset with which a non-blocking ATM switch with total throughput up to 20 Gb/s can be built. A 622 Mb/s ATM switch can be configured using a single SAM. A 10 Gb/s ATM switch using SAM/ DA/SE is illustrated.

Keywords

CMOS digital integrated circuits; asynchronous transfer mode; large scale integration; pipeline processing; 622 Mbit/s; ATM switch; CMOS; SAM; distributor/arbiter; maintenance cycle interleaved pipeline architecture; multiple ports; non-blocking ATM switch; switch access LSI; switch element; total throughput; Asynchronous transfer mode; Buffer storage; Fabrics; Forward contracts; Large scale integration; Logic; Pipelines; Switches; Throughput; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759177

Filename

759177