Design Trade-Offs in Packetizing Mechanism for Network-on-Chip

Network-on-Chip (NoC) design methodology is considered as an important trend for large System-on-Chip design because of the bandwidth and power constraints in traditional synchronous bus architecture. In the design of packet-based NoC, packetizing mechanism has great effect on communication performance, area, and energy consumption of NoC. In this paper, we carry out detailed simulation to evaluate several kinds of packetizing mechanisms of NoC based on topology of Ring and Spidergon. Simulation results show that Condition-Waiting adaptive packetizing mechanism (CW-APM) is the best trade-off packetizing mechanism in NoC design.