Implementation of a Configurable Crossbar Switch for Prototyping of Single-Chip Multiprocessors

This paper describes the implementation of a configurable crossbar switch for use as an interconnect between custom processors and cache/memory components in research prototyping of tightly-coupled single-chip multiprocessors in programmable logic. The configurability of the crossbar includes the number of ports and their width, the provision of buffering at the ports, and the complexity of the arbitration. Configuration parameters control the size of the full expansion of the crossbar from a structured, generic specification in VHDL. Results from synthesizing crossbar instances with custom 32-bit pipelined processors that have been developed in earlier multiprocessor research efforts of Manjikian (2003) are presented for configurations ranging in size from 2 times 2 to 16 times 16. With 32-bit paths for address and data, the prototyping overhead of the interconnect/arbitration logic relative to processor logic ranges from 1.2% for a 2 times 2 configuration to 55% for a large 16 times 16 configuration. For a 16 times 16 system, in particular, the crossbar and processor logic consume 73% of the logic resources in a high-capacity Altera Stratix 1S80 chip, with ample resources still available in this large chip for other components. Operational results are also provided to demonstrate the functionality of the crossbar in providing concurrent service of cache misses from multiple processors