DocumentCode :
2728713
Title :
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies
Author :
Lisbôa, C.A. ; Erigson, M.I. ; Carro, Luigi
Author_Institution :
Inst. de Informdtica, Univ. Fed. do Rio Grande do Sul, Porto Alegre
fYear :
2007
fDate :
20-24 May 2007
Firstpage :
165
Lastpage :
172
Abstract :
The evolution of the technology in search of smaller and faster devices brings along the need for a new paradigm in the design of circuits tolerant to soft errors. The current assumption of transient pulses shorter than the cycle time of the circuit will no longer be true, thereby precluding the use of most of the mitigation techniques proposed so far. With transient faults duration spanning more than one clock cycle of operation, new fault tolerance solutions, working at the system level, with low area and performance overheads, must be devised. In this paper we propose the first steps in the direction of using low cost verification schemes at the algorithmic level, applied to general purpose matrix multiplication applications. Experimental results obtained with two different implementations of checker circuits using the proposed technique are presented and discussed.
Keywords :
fault tolerant computing; transient analysis; checker circuits; long duration transient faults; matrix multiplication; mitigation; transient pulses; verification schemes; Application software; Circuit faults; Clocks; Costs; Fault tolerant systems; Frequency; Pulse circuits; Silicon; Single event upset; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2007. ETS '07. 12th IEEE European
Conference_Location :
Freiburg
Print_ISBN :
0-7695-2827-9
Type :
conf
DOI :
10.1109/ETS.2007.39
Filename :
4221590
Link To Document :
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