Title :
High frequency LNA design in Standard CMOS process
Author :
Egels, M. ; Gaubert, J. ; Pannier, P.
Author_Institution :
Dept. of Microelectron., Polytech´´ Marseille
Abstract :
The high frequency LNA design in standard CMOS process is discussed. The traditional cascode architecture is compared to the common source configuration. It is shown that at high frequency of operation the use of a common source first stage leads to a lower noise figure. Design of two K-band LNAs with lumped elements matching cells or distributed matching cells is presented in a 0.13 mum standard CMOS process. Simulations show a noise factor of 3.1 dB with a power gain of 18.6 dB for 30 mW power consumption
Keywords :
CMOS analogue integrated circuits; low noise amplifiers; microwave amplifiers; microwave integrated circuits; 0.13 micron; 18 to 27 GHz; 18.6 dB; 30 mW; CMOS process; K-band; LNA; cascode architecture; distributed matching cells; low noise amplifier; lumped elements matching cells; CMOS process; CMOS technology; Design methodology; Frequency; Inductors; K-band; Low-noise amplifiers; Noise figure; Noise reduction; Optimized production technology;
Conference_Titel :
Circuits and Systems, 2006 IEEE North-East Workshop on
Conference_Location :
Gatineau, Que.
Print_ISBN :
1-4244-0416-9
Electronic_ISBN :
1-4244-0417-7
DOI :
10.1109/NEWCAS.2006.250957
