DocumentCode :
2728767
Title :
Yield modeling of 3D integrated wafer scale assemblies
Author :
Campbell, David V.
Author_Institution :
Sandia Nat. Labs., Albuquerque, NM, USA
fYear :
2010
fDate :
1-4 June 2010
Firstpage :
1935
Lastpage :
1938
Abstract :
3D Integration approaches exist for wafer-to-wafer, die-to-wafer, and die-to-die assembly, each with distinct merits. Creation of "seamless" wafer scale focal plane arrays on the order of 6–8” in diameter drives very demanding yield requirements and understanding. This work established a Monte Carlo model of our exploratory architecture in order to assess the trades of the various assembly methods. The model results suggested an optimum die size, number of die stacks per assembly, number of layers per stack, and quantified the value of sorting for optimizing the assembly process.
Keywords :
Analysis of variance; Assembly; Equations; Laboratories; Monte Carlo methods; Production; Research and development; Semiconductor device modeling; Sorting; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th
Conference_Location :
Las Vegas, NV, USA
ISSN :
0569-5503
Print_ISBN :
978-1-4244-6410-4
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2010.5490688
Filename :
5490688
Link To Document :
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