DocumentCode
2728797
Title
Embedded Tutorial: IC Test Cost Benchmarking
Author
Luther, Klaus
Author_Institution
VP Test Technol., Infineon Technol. AG, Neubiberg
fYear
2007
fDate
20-24 May 2007
Firstpage
200
Lastpage
200
Abstract
Driven by the increasing complexity of integrated circuits, the pressure on test cost reduction increases exponentially as productivity on chip level progresses according to Moore´s Law. A high-level strategic approach for test cost target setting and planning will be explained. The intention is to keep cost of test constant relative to overall cost of goods sold. This method has been developed and used at Infineon over the last couple of years to align our location, equipment and productivity target setting.
Keywords
benchmark testing; cost reduction; integrated circuit testing; IC test cost benchmarking; Infineon; Moore´s Law; high-level strategic approach; integrated circuit complexity; test cost reduction; Benchmark testing; Best practices; Circuit testing; Costs; Integrated circuit technology; Integrated circuit testing; Productivity; Research and development; System testing; Tutorial; benchmarking; best practice; cost; test time;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2007. ETS '07. 12th IEEE European
Conference_Location
Freiburg
Print_ISBN
0-7695-2827-9
Type
conf
DOI
10.1109/ETS.2007.23
Filename
4221595
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