DocumentCode :
2728822
Title :
Embedded Tutorial on Low Power Test
Author :
Nicolici, Nicola ; Wen, Xiaoqing
Author_Institution :
Dept. of ECE, McMaster Univ., Hamilton, ON
fYear :
2007
fDate :
20-24 May 2007
Firstpage :
202
Lastpage :
210
Abstract :
Excessive power during test affects the reliability of digital integrated circuits, test throughput and manufacturing yield. Numerous low power test methods have been investigated over the past decade and new power-aware automatic test pattern generation, design-for-test and test planning techniques have emerged. This embedded tutorial introduces the topic of low power test and it overviews the basic techniques and some recent advancements in this field.
Keywords :
CMOS digital integrated circuits; automatic test pattern generation; integrated circuit reliability; integrated circuit testing; CMOS technology; complementary metal oxide semiconductor technology; design-for-test; digital integrated circuits; embedded tutorial; low power test; power-aware automatic test pattern generation; test planning techniques; Automatic test pattern generation; Automatic testing; Circuit testing; Digital integrated circuits; Integrated circuit manufacture; Integrated circuit reliability; Integrated circuit testing; Integrated circuit yield; Throughput; Tutorial;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2007. ETS '07. 12th IEEE European
Conference_Location :
Freiburg
Print_ISBN :
0-7695-2827-9
Type :
conf
DOI :
10.1109/ETS.2007.22
Filename :
4221597
Link To Document :
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