Conception of UHF voltage multiplier for RFID circuit

Author

Emmanuel, Bergeret ; Gaubert, Jean ; Pannier, Philippe ; Gaultier, Jean-Marie

Author_Institution

IMT Technopole de Chateau Gombert, Marseille

fYear

2006

fDate

38869

Firstpage

217

Lastpage

220

Abstract

This paper presents a study and an optimization of a diode voltage multiplier including antenna matching problems. Results on this multiplier designed in a 0.18mum CMOS process are shown. It can power a RFID integrated circuit at a distance of 10 m with an efficiency of 30%. In this paper a simple analytical model of the complete tag including antenna and chip is presented. This model allows explaining results on crucial points of voltage multiplier design method. A test chip is designed and realized in collaboration with ST Microelectronics. Many measures are then realized and present good agreement with simulation results

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; microwave integrated circuits; network synthesis; radiofrequency identification; voltage multipliers; 0.18 micron; 10 m; 30 percent; CMOS process; RFID circuit; ST Microelectronics; UHF voltage multiplier; antenna matching; diode voltage multiplier; Analytical models; CMOS process; Circuit testing; Collaboration; Design methodology; Diodes; Radiofrequency identification; Semiconductor device modeling; UHF circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006 IEEE North-East Workshop on

Conference_Location

Gatineau, Que.

Print_ISBN

1-4244-0416-9

Electronic_ISBN

1-4244-0417-7

Type

conf

DOI

10.1109/NEWCAS.2006.250961

Filename

4016992