Title :
Reduce SOC Energy Consumption through Processor ISA Extension
Author_Institution :
Tensilica, Inc., Santa Clara
Abstract :
The combination of reduced core operating voltage and reduced clock frequency achieved through processor core ISA extension greatly reduces the energy required to execute the task, often by one to two orders of magnitude.
Keywords :
instruction sets; system-on-chip; SOC energy consumption; instruction set architecture; reduced clock frequency; reduced core operating voltage; Acceleration; Clocks; Cryptography; Energy consumption; Frequency; Hardware; Instruction sets; Registers; Systolic arrays; Voltage;
Conference_Titel :
System-on-Chip, 2007 International Symposium on
Conference_Location :
Tampere
Print_ISBN :
978-1-4244-1368-3
Electronic_ISBN :
07EX1846C
DOI :
10.1109/ISSOC.2007.4427427
