A microprocessor with a 128 b CPU, 10 floating-point MACs, 4 floating-point dividers, and an MPEG2 decoder

High-performance arithmetic operations and high-bandwidth data stream transfers are the keys in achieving high-quality image expression for computer entertainment applications. Integrating multiple arithmetic operating units with wide internal buses is the solution. For implementation, ten floating-point multiplier-accumulators, four floating-point dividers, and an MPEG2 decoder are integrated with a CPU core on a single die. A 10-channel direct memory access (DMA) controller helps transfer the data between modules and the external main memory through 128 b width internal buses. This microprocessor comprises a MIPS architecture CPU with a floating-point coprocessor (FPU), two floating-point vector units, an MPEG2 decoding accelerator as the image processing unit (IPU), a 10-channel direct memory access (DMA) controller and other peripheral modules.