A high bandwidth superscalar microprocessor for multimedia applications

Author

Raam, F.M. ; Agarwal, Rohit ; Malik, Krystyna ; Landman, H.A. ; Tago, H. ; Teruyama, T. ; Sakamoto, Takanori ; Yoshida, Takafumi ; Yoshioka, Shohei ; Fujimoto, Yasutaka ; Kobayashi, Takehiko ; Hiroi, Takahiro ; Oka, Mitsuru ; Ohba, A. ; Suzuoki, M. ; Yuta

Author_Institution

Toshiba Corp., San Jose, CA, USA

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

258

Lastpage

259

Abstract

This 250 MHz 2-way superscalar MIPS-compatible embedded microprocessor is targeted for use in high-end consumer electronics, game, and network markets. The microprocessor features a high-bandwidth (2.0 GB/s peak) 128 b external bus. Internal datapaths and load/store paths to and from the caches are also 128 b wide. Numerous functional enhancements are incorporated, including a 128 b SIMD instruction set for multimedia support, an integrated scratchpad RAM (SPRAM), and a comprehensive set of debug and performance counting facilities.

Keywords

consumer electronics; embedded systems; instruction sets; microprocessor chips; multimedia computing; parallel architectures; 128 bit; 2.0 GB/s; 250 MHz; MIPS-compatible embedded microprocessor; SIMD instruction set; SPRAM; external bus; functional enhancements; high bandwidth superscalar microprocessor; high-end consumer electronics; integrated scratchpad RAM; internal datapaths; load/store paths; multimedia applications; performance counting facilities; Application software; Bandwidth; Computer networks; Consumer electronics; Coprocessors; Driver circuits; Embedded computing; Games; Microprocessors; Pipelines;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759231

Filename

759231