DocumentCode
2729543
Title
Room-temperature chip-stack interconnection using compliant bumps and wedge-incorporated electrodes
Author
Watanabe, Naoya ; Asano, Tanemasa
Author_Institution
Grad. Sch. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka, Japan
fYear
2010
fDate
1-4 June 2010
Firstpage
1763
Lastpage
1768
Abstract
We propose room-temperature chip-stack interconnection using mechanical caulking between compliant bumps and wedge-incorporated electrodes. In this method, cone-shaped compliant bumps made of Au are pressed into wedge-incorporated electrodes made of Au at room temperature in the ambient air. Because of the edge structures of the Au wedge incorporated electrodes, the pressing load is effectively applied to the interfaces between Au cone bumps and Au wedge-incorporated electrodes. Therefore, Au wedge-incorporated electrodes are caulked with Au cone bumps at low pressing load. By using this method, high-density inter-chip connections were realized at 0.50 gf/bump and 30 °C. The number of inter-chip connections realized was 30,600 with 20 μm pitch. It is also demonstrated that this method allows lower inter-chip connection resistance than the mechanical caulking between compliant bumps and doughnut-shaped electrodes.
Keywords
Electrodes; Gold; Information science; Integrated circuit interconnections; Lithography; Pressing; Resists; Sensor arrays; Stacking; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th
Conference_Location
Las Vegas, NV, USA
ISSN
0569-5503
Print_ISBN
978-1-4244-6410-4
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2010.5490730
Filename
5490730
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