Title :
A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 /spl mu/m 3.5 nm Tox 1.8 V CMOS technology
Author :
Sanchez, Hector Eloys ; Siegel, J. ; Nicoletta, C. ; Alvarez, J. ; Nissen, J. ; Gerosa, G.
Author_Institution :
Somerset Design Center, Motorola Inc., Austin, TX, USA
Abstract :
The continued scaling of transistor performance is delivering unprecedented microprocessor performance. However, the logic supply voltage, Vdd, is being reduced at a faster rate than the required I/O voltage level, OVDD. OVDD scales more slowly due to peripherals, which are built on mature technologies that require higher OVDD. Time-to-market constraints and chip integration issues further impose a single I/O driver as the desired solution. The I/O driver must meet the reliability constraints of the 3.3 V interface with a transistor that has a 3.5 nm Tox (no dual-gate oxide processing step). The 128b L2 interface must run at 400MHz clock rate and the 128b system interface at 150MHz. Both interfaces are compatible with the 3.3V/2.5V interfaces ofthe PowerPC TM 750, yet support more aggressive 1.8V systems.
Keywords :
CMOS digital integrated circuits; driver circuits; integrated circuit reliability; microprocessor chips; 0.2 micron; 1.8 V; 2.5 V; 3.3 V; 3.5 nm; 400 MHz; CMOS I/O driver; I/O voltage level; L2 interface; PowerPC TM 750; chip integration issues; logic supply voltage; microprocessor performance; reliability constraints; single I/O driver; system interface; time-to-market constraints; transistor performance; Application specific integrated circuits; CMOS technology; Copper; Degradation; Driver circuits; Integrated circuit interconnections; Integrated circuit technology; Random access memory; Solid state circuits; Trademarks;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759244
