DocumentCode
2729645
Title
A New Look at Reversible Logic Implementation of Decimal Adder
Author
James, Rekha K. ; Shahana, T.K. ; Jacob, K. Poulose ; Sasi, Sreela
Author_Institution
Cochin Univ. of Sci. & Technol., Kochi
fYear
2007
fDate
20-21 Nov. 2007
Firstpage
1
Lastpage
4
Abstract
Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. This research proposes a new implementation of Binary Coded Decimal (BCD) adder in reversible logic. The design reduces the number of gates and garbage outputs compared to the existing BCD adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay.
Keywords
adders; binary codes; logic design; logic gates; low-power electronics; BCD; binary coded decimal adder; garbage output; logic gate; low power CMOS; minimal energy dissipation; nanotechnology; power optimization; quantum computing; reversible logic design; Adders; CMOS logic circuits; Delay; Jacobian matrices; Logic circuits; Logic design; Logic devices; Logic gates; Quantum computing; Temperature; BCD adder; decimal arithmetic; reversible logic;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2007 International Symposium on
Conference_Location
Tampere
ISSN
07EX1846
Print_ISBN
978-1-4244-1367-6
Electronic_ISBN
07EX1846
Type
conf
DOI
10.1109/ISSOC.2007.4427442
Filename
4427442
Link To Document