Title :
Sense amplifier-based flip-flop
Author :
Nikolic, B. ; Stojanovic, V. ; Oklobdzija, V.G. ; Wenyan Jia ; Chiu, Justin ; Leung, Martin
Author_Institution :
Storage Products Group, Texas Instrum., San Jose, CA, USA
Abstract :
Timing elements, latches and flip-flops, are critical to performance of digital systems, due to tighter timing constraints and low power requirements. Short setup and hold times are essential, but often overlooked. Recently reported flip-flop structures achieved small delay between the latest point of data arrival and output transition. Typical representatives of these structures are sense amplifier-based flip-flop (SAFF), hybrid latch-flip-flop (HLFF) and semi-dynamic flipflop (SDFF). Hybrid flip-flops outperform reported sense amplifier-based designs, because the latter are limited by the output latch implementation. SAFF consists ofthe sense amplifier in the first stage and the RS latch in the second stage.
Keywords :
flip-flops; low-power electronics; sequential circuits; timing; RS latch; data arrival; flip-flop structures; hold times; hybrid latch - flip-flop; low power requirements; output latch implementation; output transition; semi-dynamic flipflop; sense amplifier-based flip-flop; setup times; timing constraints; CMOS technology; Circuit topology; Clocks; Delay effects; Flip-flops; Latches; Logic; Master-slave; Switches; Timing;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759251
