Asynchronous sense differential logic

Charge-recycling differential logic (CRDL) implements energy-efficient operation by recycling already used charge. This technique requires p-channel devices with higher threshold for maximum efficiency. Half-rail differential logic (HRDL) avoids the drawback at the expense of performance. These circuits are prone to pre-evaluation discharge during evaluation when not properly designed. Asynchronous sense differential logic (ASDL) improves energy efficiency with no threshold change or performance degradation.