A Study of Sulphur Assisted Corrosion in Technologies with Copper Interconnects

Increased packing density and reduced device size leads to increase in the back-end related delays. This happens as a result of increase in the metal resistance due to decreased line-width and increased capacitance due to a higher density of the interconnects. To minimize the impact of interconnect related delays (RC delay) the semiconductor industry had to, as a first order change, look for metal with a lower sheet resistance. Copper being material with lower sheet resistance, was chosen for the interconnect purposes. In the dual damascene approach to copper interconnect patterning, capping of copper after the copper CMP process is very important. It is well know that copper, when exposed to air, corrodes. Different types of copper corrosion phenomena are described in literature. Copper also diffuses into the dielectric causing shorts or leakages between the adjacent metal lines. A Si₃N₄ or SiC capping layer is, therefore, deposited almost immediately after the copper CMP process. These dielectric capping layers are found to be good barriers for copper diffusion/corrosion. In a manufacturing environment, it is practically impossible to cap the freshly exposed copper surface, immediately, by depositing the dielectric barrier due to time constraint. Batches of wafer are kept in a neutral ambient like the N2 ambient, to prevent copper corrosion from happening, before the dielectric barrier deposition. After careful study, a time-link is established between the deposition of the dielectric barrier and the copper CMP process. The dielectric barrier is supposed to be deposited within the time established by the "time-link" to prevent the copper from corroding. In this paper, a new copper corrosion mechanism is reported which is found to be sulphur assisted