Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systems

In the next years, multi-processor systems-on-chip (MPSoC) are expected to become the platform of choice for new feature-rich devices in high-volume markets like wireless telecom and portable multi-media. With increasing chip densities and an ever growing quest for both more functionality and longer battery autonomy, low energy consumption becomes of the essence in the design of these SoCs. The International Roadmap for Semiconductors (ITRS) shows that the power budget (allowable consumption in Watts) for chips for battery-powered hand-held systems will remain constant in the next decade. The reduction of technology geometries will not automatically result in significant power savings because of the growing importance of static (or leakage) power. Therefore, new architectural methodologies are indispensable to meet the power challenges of SoCs. In this presentation we will review architectural strategies for the design of ultra-low power SoCs. Drawing from experience in power-sensitive market segments like hearing instruments, we contend that MPSoC architectures must be heterogeneous to meet the ultra-low power requirements of next-generation telecom and multi-media systems. Rather than replicating identical processor cores and let them communicate via a general-purpose on-chip network, we propose that each processor core as well as the communication network is optimised for the application. This provides for an optimal balance of arithmetic units, and both task-level, data-level, and instruction-level parallelism, resulting in lowest energy consumption. Multi-core SoCs based on application-specific instruction-set processors (ASIPs) thus allow to push the power envelope to the next level.