Implementation tradeoffs of triangle traversal algorithms for graphics processing

Current CPU architectures provide high processing rates in graphical applications because of their specialized graphics pipeline. So far, little attention has been paid in the scientific literature to the analysis and study of different hardware structures that implement specific pipeline stages. In this work we have identified one of the key stages in the graphics pipeline, the triangle traversal procedure, and we have implemented it in a 90 nm standard cell technology, comparing three different algorithms: Bounding-box, Zig-zag and Hilbert curve-based. The experimental results show that important area-latency-frequency-throughput tradeoffs must be taken into account for the implementation of the triangle traversal stages. Furthermore, since power is a main concern in CPUs, we have studied how some triangle characteristics such as the shape, size, position and depth affect the power consumption.