Power delivery system architecture for many-tier 3D systems

Many-tier systems are the future of 3D integration. In this work we explore power delivery system design for these large scale devices. We have developed a scalable many-tier design that contains one tier of processors and eight tiers of DRAM. These nine tiers comprise a ´set´ that can be stacked any number of times. Previously, we have examined the dynamic and static power noise scaling behavior of various components of this system. Now, we present studies on two key aspects of power system architecture in these systems and their impact on power supply noise. First, we examine the addition of a dynamic noise-limiting turn-on policy and show that it can reduce dynamic power supply noise by 37% with almost no impact on system performance. Next, we present interesting results comparing different power/ground TSV topologies and show that a spread TSV distribution can lower both DC and dynamic power supply noise in the case that the many-tier stack contains low power tiers, such as memory tiers. We also show that ignoring TSV inductance when calculating dynamic noise can result in a 14.8% underestimate.