A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD

The linearity of analog-to-digital converters (ADCs) is often limited by component mismatches. Trimming can be used to achieve high linearity but cannot track variations over time caused by component aging or by temperature and power-supply changes. Background calibration overcomes this limitation. However, previous background-calibration methods require complicated post processing, occupy some of the range of the analog signal under conversion, or are tailored for a specific type of converter. This ADC uses a queue-based architecture for creating calibration time slots without disturbing the sampling of the input signal. The digital background calibration uses an adaptive algorithm to improve linearity. The queue-based architecture for generating the calibration time slots and the digital-background-calibration method are independent and can be used separately.