A 3.3 V 10 b 25 Msample/s two-step ADC in 0.35 /spl mu/m CMOS

System-on-chip for video, QAM and VSB applications requires analog-to-digital converters (ADC) in state-of-the-art CMOS technology. The untrimmed ADC is realized in standard single poly 0.35 /spl mu/m CMOS technology with 3.3 V supply voltage, dissipates 195 mW and measures 0.8 mm/sup 2/, including track-and-hold and clock-generation circuits. This ADC achieves 9.3 ENOB with an effective resolution bandwidth of 14 MHz at 16 MSample/s sample frequency. The ADC is based on a two-step architecture, which combines a high sampling rate with a limited number of comparators. This ADC operates at 3.3 V supply voltage by using a floating ladder structure, full differential dual residue signal processing with improved switching and offset-compensated residue amplifiers. Latency is kept at a minimum of 2 cycles.