Minimum power loss for high-side power MOSFETs in DC-DC converter with TBO and high cell density

Author

Hun, Jeong Yong ; Ngo, Bong Bui ; Han, Chai Sian

Author_Institution

X-FAB Sarawak Sdn. Bhd., Kuching, Malaysia

fYear

2011

fDate

25-28 Sept. 2011

Firstpage

178

Lastpage

181

Abstract

For the Synchronous DC-DC converter switching performance of low-voltage power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Ron.sp) and Qgd is commonly used to quantify the switching performance for a specified off-state breakdown voltage (BVds). Two approaches are taken to reduce the Ron.sp & Qgd. First is by shrinking the trench gate width to increase the cell densities up to 645Mcell/inch² for an ultra low on state resistance using 0.18um design rule process. The other is to obtain lower Qgd with thick bottom oxide (TBO) at minimum trench gate width by double HDP processing. The results shows that the reduce Qgd 36%, total Qg[Vgs=10V] 27% and Qg uniformity around 7% within wafer.

Keywords

DC-DC power convertors; electric breakdown; power MOSFET; switching convertors; BVds; Qgd; TBO; design rule process; double HDP processing; figure-of-merit; gate-drain charge density; high cell density; low-voltage power MOSFET; off-state breakdown voltage; power loss; ron.sp; size 0.18 mum; specific on-resistance; synchronous DC-DC converter switching performance; thick bottom oxide; trench gate width shrinking; Capacitance; Immune system; Logic gates; MOSFETs; Resistance; Silicon; Switches; DC-DC converter; Gate charge density; Thick bottom oxide; Trench Power MOSFET; Ultra low RDS(ON);

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics and Applications (ISIEA), 2011 IEEE Symposium on

Conference_Location

Langkawi

Print_ISBN

978-1-4577-1418-4

Type

conf

DOI

10.1109/ISIEA.2011.6108692

Filename

6108692