A 65 mW 10 b 40 Msample/s BiCMOS Nyquist ADC in 0.8 mm/sup 2/

This ADC is to be embedded in video-signal-processing ICs. Because this integration is mixed-signal, focus during architectural and circuit design is on low power, low area consumption and low substrate noise sensitivity and generation. The 10 b ADC is based on a cascaded folding and interpolating architecture. Folding and interpolating factors are optimized for low power and low area. The circuit fully exploits the available 5 V supply by means of stacked folding topologies and dimensioning is based on balancing trade-off parameters for the various devices and stages. The untrimmed ADC achieves Nyquist performance at 40 MSample/s: the input frequency, where half an effective bit is lost compared to low input frequency performance, is 20 MHz. The low input frequency performance is 9.2 effective bits. The 0.8 mm/sup 2/ ADC is in 7 GHz, 0.6 /spl mu/m BiCMOS and dissipates 65 mW from a single 5 V supply.