Title :
A 75 mW 10 b 20 MSample/s CMOS subranging ADC with 59 dB SNDR
Author :
Brandt, Brian ; Lutsky, J.
Author_Institution :
Nat. Semicond. Corp., Salem, NH, USA
Abstract :
In a two-step CMOS subranging ADC (CSA), a coarse comparator bank determines which subset of fine reference taps from a resistor ladder should be passed (without amplification or subtraction from the ADC input) to a fine comparator bank by an analog multiplexer (AMUX). This CSA provides advantages over previously-reported variations of this architecture. These advantages include absolute value signal processing, an extended settling period for the fine references, a fully differential topology, and a front-end sample-and-hold amplifier (SHA). As a result of these features, this ADC achieves 9.5 ENOB Nyquist performance at 75 mW and two-clock-cycle conversion latency.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); sample and hold circuits; 10 bit; 75 mW; CMOS; Nyquist performance; SNDR; absolute value signal processing; analog multiplexer; coarse comparator bank; extended settling period; fine comparator bank; fine reference taps; fully differential topology; sample-and-hold amplifier; subranging ADC; two-clock-cycle conversion latency; two-step architecture; CMOS technology; Capacitance; Clocks; Delay; Electrostatic discharge; Solid state circuits; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759270
