Title :
A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique
Author :
Kwangho Yoon ; Sungkyung Park ; Wonchan Kim
Author_Institution :
Seoul Nat. Univ., South Korea
Abstract :
A 6 b 500 MSample/s Flash ADC employs interpolated auto-zeroing carried out in background mode. To improve the ADC differential nonlinearity characteristic, a resistor network with its inherent error averaging property is employed for interpolation.
Keywords :
CMOS integrated circuits; analogue-digital conversion; interpolation; 6 bit; CMOS; background interpolated auto-zeroing technique; differential nonlinearity characteristic; error averaging property; flash ADC; resistor network; Bandwidth; Calibration; Circuits; Interpolation; Joining processes; Resistors; Switches; Timing; Voltage; Working environment noise;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759274
