Title :
Novel method for debug of electrostatic discharge protection in VLSI circuits
Author :
Sofer, Sergey ; Fefer, Yefim ; Borenshtein, Mariana ; Shapira, Yoram
Author_Institution :
Freescale Semicond. Israel Ltd., Herzelia
Abstract :
A proposed method for failure analysis and debugging of electrostatic discharge protection in VLSI circuits is presented, based on low-energy non-destructive emulation of real ESD stress. It allows on-die current and voltage measurements during stress, providing a direct and clear conclusion about the proper functioning of the protection method, or a reason for failure
Keywords :
VLSI; electrostatic discharge; failure analysis; integrated circuit reliability; ESD stress; VLSI circuits; electrostatic discharge protection; failure analysis; low-energy non-destructive emulation; Circuit testing; Debugging; Electrostatic discharge; Electrostatic interference; Failure analysis; Integrated circuit testing; Protection; Shape; Stress; Very large scale integration;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2006. 13th International Symposium on the
Conference_Location :
Singapore
Print_ISBN :
1-4244-0205-0
Electronic_ISBN :
1-4244-0206-9
DOI :
10.1109/IPFA.2006.251043
