CMOS PA design dedicated to UMTS (3G) applications in 65 nm technology

Author

Luque, Y. ; Kerherve, E. ; Deltimple, N. ; Belot, D.

Author_Institution

IMS Lab., Univ. de Bordeaux, Talence

fYear

2008

fDate

10-11 July 2008

Firstpage

101

Lastpage

104

Abstract

This paper deals with the challenges of designing and implementing a PA dedicated to 3G applications in a CMOS 65 nm technology. High linearity and high power applications impose several bottlenecks from the layout point of view. The difficulties are increased by the use of a low cost technology. Reduce the size of the circuit while increasing the power leads to think of a different layout topology. The PAE (power added efficiency) in this type of application is generally low, making the thermal effect, even more critical. The layout will be used as an example to highlight the compromises that have been made along the process. Thanks to a new PA structure and a very carefully layout, this CMOS power amplifier provides a 31 dBm maximal output power with a PAE of 25% at 1.95 GHz.

Keywords

3G mobile communication; CMOS analogue integrated circuits; UHF power amplifiers; network topology; 3G applications; CMOS PA design; CMOS power amplifier; CMOS technology; UMTS applications; layout topology; power added efficiency; size 65 nm; thermal effect; 3G mobile communication; CMOS technology; Circuits; Costs; Linearity; Multiaccess communication; Paper technology; Power amplifiers; Power generation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems for Communications, 2008. ECCSC 2008. 4th European Conference on

Conference_Location

Bucharest

Print_ISBN

978-1-4244-2419-1

Electronic_ISBN

978-1-4244-2420-7

Type

conf

DOI

10.1109/ECCSC.2008.4611655

Filename

4611655