DocumentCode
2730281
Title
A 1 Gb/s CMOS clock and data recovery circuit
Author
Hui Wang ; Nottenburg, R.
Author_Institution
Univ. of Southern California, Los Angeles, CA, USA
fYear
1999
fDate
17-17 Feb. 1999
Firstpage
354
Lastpage
355
Abstract
So far, high-speed CMOS clock and data recovery (CDR) circuits usually use a multi-phase oversampling technique that has limited acquisition range and requires a reference clock. The Gb/s CMOS CDR in this paper does not need any reference clock input. The CDR achieves a wide acquisition range of /spl plusmn/200 MHz and small RMS jitter of 7.4 ps (0.0074 UI) in the recovered 1 GHz clock.
Keywords
CMOS digital integrated circuits; digital phase locked loops; high-speed integrated circuits; jitter; synchronisation; 1 Gbit/s; 7.4 ps; CDR; RMS jitter; acquisition range; clock recovery circuit; data recovery circuit; high-speed CMOS; 1f noise; Circuit optimization; Clocks; Detectors; Frequency locked loops; Jitter; Phase locked loops; Quantum cascade lasers; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-5126-6
Type
conf
DOI
10.1109/ISSCC.1999.759292
Filename
759292
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