Asynchronous to synchronous: A design methodology

This paper presents the methodology of converting an asynchronous design to a synchronous design. As the size of transistor is shrinking, the difficulty of a design to meet the timing has increased. Continuously shrinking of transistor size from time to time has increased the on-die variation such as Process, Voltage, and Temperature (PVT) variation of the chip. Since Performance Verification (PV) or Static Timing Analysis (STA) tools is unable to accurately calculate the timing of asynchronous design, asynchronous design is required to migrate to synchronous based design for the STA tools to ensure the silicon timing can be met across PVT. A proper design methodology of converting asynchronous design to synchronous design is proposed in this paper. An Intel 8254 Programmable Interval Timer (PIT) is used as a case study. Current Intel 8254 timer is an asynchronous based design and it has approximately 12,000 gates. STA is performed after conversion and results shows the timing of synchronous design can be fully verified by STA. Additional comparison for area is made as well.