Title :
Cone extraction technique for incremental static timing analysis
Author :
Ang Lay Sean ; Rosdi, Bakhtiar Affendi ; Tee Kok Tiong
Author_Institution :
Univ. Sains Malaysia (USM), Minden, Malaysia
Abstract :
As design size gets larger and becomes more complicated with feature integration, the runtime for Static Timing Analysis (STA) becomes more of a concern. Due to time-to-market pressure, the validation of the design is performed in parallel with the physical synthesis flow; therefore it is not uncommon to find last minute critical logic bugs during final design integration iterations. However, timing verification needs to be run on full-chip level to ensure that the check is comprehensive. This paper proposes a method to isolate only those logics which are affected by the Engineering Change Order (ECO) for STA. This simplification will allow faster ECO iteration to enable a more efficient timing convergence. The proposed method is also suitable to be used for multithreading in STA engines to speed-up timing verification due to ECO changes.
Keywords :
iterative methods; logic circuits; microprocessor chips; timing circuits; STA engines; cone extraction; critical logic bugs; design integration iterations; engineering change order iteration; feature integration; full-chip level; incremental static timing analysis; multithreading; physical synthesis flow; time-to-market pressure; timing convergence; timing verification; Capacitance; Data mining; Delay; Integrated circuit interconnections; Logic gates; Pins;
Conference_Titel :
Industrial Electronics and Applications (ISIEA), 2011 IEEE Symposium on
Conference_Location :
Langkawi
Print_ISBN :
978-1-4577-1418-4
DOI :
10.1109/ISIEA.2011.6108713