Ultra thin die embedding technology with 20μm-pitch interconnection

A novel approach is presented for polymer die embedding and 3D stacking technology, applicable to 3D LSI packaging with consideration to future die specifications. Two main parts are described here; a newly developed die thinning process and an integration process employing via opening by deep reactive ion etching (DRIE). The target minimum pad pitch on embedded dies was 20 µm, considering the finest pad pitch in the next 5 to 10 years. Thin dies embedded in polymer allow for the use of narrow-pitch copper pillars beside the dies for vertical conductive connections. 20 µm-pitch pads on approximately 15 µm-thick die were successfully connected using such 3D interconnections to a base wafer, and confirmed by electrical measurements.