A fault-detecting 400 MHz floating-point unit for a massively-parallel computer

Author

Ohkubo, N. ; Kawashimo, T. ; Suzuki, M. ; Suzuki, Yuya ; Kikuchi, J. ; Tokoro, M. ; Yamagata, Ryosuke ; Kamada, E. ; Yamashita, Takayoshi ; Shimizu, Tsuyoshi ; Hashimoto, Toshikazu ; Isobe, Takanori

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

368

Lastpage

369

Abstract

Even if the error rate of a single processor is low, that of a computer using thousands of parallel processors will not be negligible. A fault-detecting floating-point unit in a CMOS RISC microprocessor for a parallel computer solves the problem. This floating-point unit is equipped with small-area fault detectors and achieves 92% fault-detection rate with 18% area overhead in a multiply-add unit. The floating-point unit uses 0.25 /spl mu/m CMOS technology and it achieves 1.6 GFLOPS at 400 MHz and 1.8 V supply.

Keywords

CMOS digital integrated circuits; fault diagnosis; floating point arithmetic; microprocessor chips; parallel architectures; reduced instruction set computing; 0.25 micron; 1.6 GFLOPS; 1.8 V; 400 MHz; CMOS; RISC microprocessor; area overhead; fault-detecting unit; fault-detection rate; floating-point unit; massively-parallel computer; multiply-add unit; parallel processors; small-area fault detectors; CMOS technology; Concurrent computing; Data conversion; Decoding; Error analysis; Fault detection; Laboratories; Logic; Parity check codes; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759299

Filename

759299