DocumentCode
2730430
Title
Recursive parallel interleavers for two-phase error control decoders
Author
Ahmed, Itman ; Vithanage, Cheran ; Ismail, Mahamod ; McGeehan, Joe ; Lucas, David
Author_Institution
Telecommun. Res. Lab., Toshiba Res. Eur. Ltd., Bristol, UK
fYear
2010
fDate
6-10 Sept. 2010
Firstpage
58
Lastpage
62
Abstract
A new memory mapping technique using a VLSI circuit based on recursive quadratic polynomial equations is described. The proposed methodology allows parallel processing elements, such as used in Turbo and Low Density Parity Check (LDPC) decoders, to work independently across memory segments, thus enabling parallel, high throughput, and power efficient LSI circuits.
Keywords
VLSI; decoding; error correction codes; interleaved codes; parallel architectures; parity check codes; polynomials; turbo codes; Turbo decoder; VLSI circuit; low density parity check decoder; memory mapping technique; parallel processing; power efficient LSI circuit; recursive parallel interleaver; recursive quadratic polynomial equation; two-phase error control decoder; CMOS integrated circuits; Laboratories; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Turbo Codes and Iterative Information Processing (ISTC), 2010 6th International Symposium on
Conference_Location
Brest
Print_ISBN
978-1-4244-6744-0
Electronic_ISBN
978-1-4244-6745-7
Type
conf
DOI
10.1109/ISTC.2010.5613873
Filename
5613873
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