Title :
Process, fabrication, and characteristics of a 0.8 μm CMOS triple-level-metal gate array
Author :
Manos, Pete ; Smith, Brad ; Chang, K.Y. ; Klein, Jeff ; Pintchovski, Fabio ; Travis, Ed ; Woo, Michael ; Lai, Steve ; Dillard, Rick
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
A 0.8-μm CMOS (complementary metal-oxide-semiconductor) triple-level-metal ASIC (application-specific integrated circuit) technology has been developed. Features of this process include heavy twin-well architecture, improved LOCOS (local oxidation of silicon) isolation, scaled gate oxide thickness, and enhanced channel implants. The advanced triple-level-metal module includes a high-temperature contact barrier, dry-dry tapered contacts and vias, and planarized plasma TEOS interlevel dielectric. Inverter gate delays of 110 ps have been demonstrated on a 16 K gate array
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; invertors; logic arrays; 0.8 micron; 110 ps; ASIC; CMOS triple-level-metal gate array; LOCOS; dry-dry tapered contacts; enhanced channel implants; heavy twin-well architecture; high-temperature contact barrier; planarized plasma TEOS interlevel dielectric; scaled gate oxide thickness; vias; Application specific integrated circuits; CMOS process; CMOS technology; Fabrication; Implants; Integrated circuit technology; Isolation technology; Oxidation; Plasma applications; Silicon;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68614
