A SiGe single-chip 3.3 V receiver IC for 10 Gb/s optical communication systems

Author

Morikawa, T. ; Soda, M. ; Shioirl, S. ; Hashimoto, Toshikazu ; Sato, Fumiaki ; Emura, Keita

Author_Institution

C&C Media Res. Labs., NEC Corp., Kawasaki, Japan

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

380

Lastpage

381

Abstract

A SiGe single-chip 3.3 V receiver IC for 10 Gb/s optical communication systems integrates a transimpedance preamplifier, a limiting amplifier with a reference voltage generator, and a clock and data recovery (CDR) circuit with a phase-locked loop (PLL). For this IC, phase-comparison automatically adjusts the clock phase to the optimum point for data regeneration in the CDR circuit. The receiver IC uses a SiGe bipolar transistor with 60 GHz cutoff frequency. It operates at 10 Gb/s with 660 mW power consumption at 3.3 V.

Keywords

Ge-Si alloys; integrated optoelectronics; optical fibre communication; optical receivers; phase locked loops; preamplifiers; semiconductor materials; synchronisation; 10 Gbit/s; 3.3 V; 60 GHz; 660 mW; SiGe; clock and data recovery circuit; clock phase; cutoff frequency; data regeneration; limiting amplifier; optical communication systems; phase-locked loop; power consumption; reference voltage generator; single-chip receiver IC; transimpedance preamplifier; Clocks; Germanium silicon alloys; Optical fiber communication; Optical receivers; Phase locked loops; Photonic integrated circuits; Preamplifiers; Semiconductor optical amplifiers; Silicon germanium; Stimulated emission;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759304

Filename

759304