A MOST-Only R-2R ladder-based architecture for high linearity DACs

The paper presents a MOST-Only, digitally calibrated DAC architecture, based on the R-2R ladder topology. The proposed DAC architecture employs circuitry that enables the fine trimming of each bitpsilas current contribution at the DACpsilas output, thus concluding in a high linear DAC architecture. The architecture of the proposed DAC is discussed in details along with simulation results that confirm its high linearity performance. The proposed DAC topology maintains the conventional ladderpsilas performance in speed and power dissipation without requiring large area for its implementation.