Title :
A 800 MB/s 72 Mb SLDRAM with digitally-calibrated DLL
Author :
Paris, L. ; Benzreba, J. ; De Mone, P. ; Dunn, M. ; Falkenhagen, L. ; Gillingham, P. ; Harrison, I. ; He, W. ; Macdonald, D. ; MacIntosh, M. ; Millar, B. ; Kang Wu ; Hak-June Oh ; Stender, J. ; Chen, V. ; Wu, J.
Author_Institution :
MOSAID Technol. Inc., Kanata, Ont., Canada
Abstract :
This 72 Mb synchronous-link DRAM (SLDRAM) is a proof-of-concept vehicle for next-generation memory. SLDRAM is a packet-protocol-based memory that employs source-synchronous busses with push-pull I/O for signaling integrity. SLDRAM devices are calibrated on power-up by the memory controller so individual memory devices do not have to meet tight timing specifications and compensate interconnect and loading variations.
Keywords :
DRAM chips; calibration; protocols; timing; 72 Mbit; 800 MB/s; SLDRAM; digitally-calibrated DLL; interconnect variations; loading variations; memory controller; next-generation memory; packet-protocol-based memory; power-up calibration; push-pull I/O; signaling integrity; source-synchronous busses; synchronous-link DRAM; timing specifications; Clocks; Delay lines; Electronics industry; FETs; Helium; Jitter; Random access memory; Temperature; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5126-6
DOI :
10.1109/ISSCC.1999.759329
